Search found 5 matches
- Sun Sep 13, 2015 11:24 am
- Forum: Circuit Talk
- Topic: Yet another RISC CPU
- Replies: 8
- Views: 19932
Re: Yet another RISC CPU
Hi Hans. I have replied in pm.
- Sun Jul 26, 2015 4:25 am
- Forum: Circuit Talk
- Topic: Yet another RISC CPU
- Replies: 8
- Views: 19932
Re: Yet another RISC CPU
Yes, I allow public editing for people to have some fun with it.
I have no more software examples, I have switched to implement a hardware multiplier (radix 4 booth), I have almost finished it, then stopeed due to no free time. But if people is interested I can post it.
I have no more software examples, I have switched to implement a hardware multiplier (radix 4 booth), I have almost finished it, then stopeed due to no free time. But if people is interested I can post it.
- Mon Jun 22, 2015 11:03 pm
- Forum: Circuit Talk
- Topic: Yet another RISC CPU
- Replies: 8
- Views: 19932
Re: Yet another RISC CPU
By the way, there is a more traditional macro assembler, where you can define your instructions in it. You can try it: https://bitbucket.org/EugeneLepekhin/fusion/downloads you will need to download Fusion.zip file. There is a documentation file there.
Thanks, I will give it a try.
BTW, speaking ...
Thanks, I will give it a try.
BTW, speaking ...
- Sat Jun 20, 2015 11:19 pm
- Forum: Circuit Talk
- Topic: Yet another RISC CPU
- Replies: 8
- Views: 19932
Re: Yet another RISC CPU
Here are the real instructions implemented in the CPU:
ld, st -> Load / Store indirect through register and offset e.g. ld r2, r1, 5 (r2 = Mem[r1 + 5])
add, sub, and, or, xor, shl, shr, rol, ror -> 3 registers ALU op e.g. add r1, r2, r3 (r1 = r2 + r3)
add, and, or, xor -> immediate ALU op e.g ...
ld, st -> Load / Store indirect through register and offset e.g. ld r2, r1, 5 (r2 = Mem[r1 + 5])
add, sub, and, or, xor, shl, shr, rol, ror -> 3 registers ALU op e.g. add r1, r2, r3 (r1 = r2 + r3)
add, and, or, xor -> immediate ALU op e.g ...
- Fri Jun 19, 2015 11:04 pm
- Forum: Circuit Talk
- Topic: Yet another RISC CPU
- Replies: 8
- Views: 19932
Yet another RISC CPU
I have downloaded your very nice simulator few weeks ago and I had fun writing some stuff that I'd like to share for interested people.
It is a very simple CPU, harvard style, 8 bit registers (4 registers with r0 set at zero) and 16 bit instructions, all instructions execute in 2 cycles. The most ...
It is a very simple CPU, harvard style, 8 bit registers (4 registers with r0 set at zero) and 16 bit instructions, all instructions execute in 2 cycles. The most ...