I have discovered a phenomenon that does not align with my understanding. Is it a bug?

[677]

As shown in the figure, there is a clock, an 8-bit counter, an 8-bit unsigned comparator, an 8-bit combination switch, and a T-trigger. I think the situation is that when the circuit is running, first set the binary bits of the 8-bit switch, and then click the clear button to set the counter to 0. Under clock drive, the value of the counter will eventually be equal to the value of the 8-bit switch. At this time, the output of the 8-bit unsigned comparator is 1. Since the T-trigger is also connected to the output of the comparator, the output of the T-trigger is also 1, Afterwards, although the value of the counter will be greater than the value of the 8-bit switch, causing the comparator output to become 0, the output of the T trigger will remain at 1 due to its rising edge triggering.
However, the actual situation is that when the 8-bit switch is set to an odd value, it conforms to the situation I described above. On the contrary, when the 8-bit switch is set to an even value, the output of the T trigger will become 0 at a later time. Why is this?

[admin]

Can you share your project file? It is hard to see what is going on from just a picture.

[677]

This is my project file

[admin]

Well, the problem is synchronization of your circuit.
First, your flip-flops are not raising edge triggering they are level triggering. To fix it I’ve changed it to rear edge triggering. But it turns out not enough too, I also AND the output of comparator with clock. Now it appears to be working.