Hello.
I try to realize an interrupt request circuit. My first idea was to use a SR Latch to store that an irq was send. I'm use a priority decoder to decode the intern interrupt id. On the raising edge of the clock, the flipflop save the inverted oe output (which is low if any input is high). The priority decoders main data output should save too, but I don't do this in this mini-circuit. On the falling edge, an in a rom microcoded encoder (the reverse function for the decoder) should reset the latch. But this idea cause in a oscillation, if the button is a clock cycle pressed. I know why, but I have no idea how this is realizable. I think I think to complicated. ^^
One option is to use edge triggered flip-flop instead of SR latch.
If you still have problems with your circuit maybe you can upload it here so people can have more ways to experiment and help you.
In my opinion, you don't really know the concept of interrupts. Feel free to correct me if I'm wrong.
Here you have, in a nut-shell, the stuff you need to know.
1. Interrupts are level-triggered or edge-triggered (The desired possibility is programmable.)
2. Don't control the interrupt-line directly, but control the output of the SR-latch. In this way an interrupt won't be lost.
3. The priority of the lines is controlled by the software.
4. You also need a mask to decide, which interrupt is permitted.
5. Also you need a register, where the pending interrupt will be saved.
6. The software will end the interrupt, when the right service-routine has finished.
When, you do this, your way, by hardware, oscillation occurs.
7. The software also determines, if a running service-routine may be interrupted by an other interrupt (priority)
This is done, by sending control-words to the interrupt-controller
Shortly:
An interrupt, starts an Interrupt-Service Routine (this is a kind of subroutine, a subroutine will be started by software).
An ISR, has also often a special kind of Return, called RETI, instead of RET. A RETI tells the Interrupt Controller that a new Interrupt will be granted.
So an Interrupt with a certain priority can start its ISR. An Interrupt with a higher priority will interrupt a pending ISR.
When The higher interrupt has been served, the pending interrupt will be finished.
An Interrupt with a lower priority has to wait untill, the former interrupt has been served.
Furthermore, instructions for disabling or enabling do exist. These instructions DI and EI, can be put in an ISR.
to make sure, that a pending interrupt cannot be interrupted.
Feel free, to ask me anything, but be so kind to upload a complete circuit. This makes it much easier to help you.
Of course you can design your own controller, and then you'll certainly upload your design.
Thank you very much.
On the Gameboy (modificated Z.80), the only architecture which I know "good", nothing but the interrupt enable and mask is controlled by software. The CPU call every time an interrupt occured and he is enabled a fixed memory offset and interrupt requests have fixed priorities.
I have uploaded my current project and I think, the way I've used isn't bad: viewtopic.php?f=3&t=9653
