Help With my Processor

[Xaetral]

So, I didn't talked about my processor here, and I won't do that today, sorry (I wait to finish the website and update my compiler first). I'm actually working on the third version of my architecture and I just have a small problem that prevents me from finishing my instruction decoder :/

the thing is, in this 3rd version, each instruction only needs 1 clock cycle, that works for any instruction in almost any case; yeah "almost" because I have very specific case that I can't figure out how to deal with, let me explain:

I have some conditional jumps inspired from the game "TIS-100": JEZ, JNEZ, JGZ and JLZ where the processor will jump to a provided adress if the provided register is equal to zero, not equal, greater than or smaller than, so in one use of these instructions, I can have 2 different registers given as parameters: the register in witch the adress to jump to is stored, and the register to check.

and so there's the problem: I need to access 2 registers in one single clock cycle

if I'm right (I can't tell because I never found anything on internet) the memory used in program memory or registers can't be read at 2 adresses in a single read step, I mainly want to talk about that.

I found a way to deal with that for the superscalar executions (not yet in my processor, I plan to use it on a future 32b architecture) but I can't with the registers :/

[admin]

Hi,
If I am correctly understanding your question you are trying to use memory component as registers inside CPU. Now with your jump command you need to access two registers in the same clock cycle. This is not possible with LogicCircuit memory module.
To be able to achieve your goal you have two options. In your implementation of the register block you can use two memory modules and always write in both in parallel and read from each one individually. Or you build your registers from flip-flops and then you can access them in whatever manner you want.
Hope that help,
Eugene

[Xaetral]

well, sorry, I forgot to mention that I'm already thinking about the transistor implementation, the thing is that I wonder if it's possible to add a second selection matrix on the silicon die of a memory.

and in the software, I very far from using memory modules or even matrix ^^'


edit: YES this madness works prefectly fine XDDD

[admin]

Well, I it is going to be much easier to design, debug and understand your circuit if you modularize it.

[Xaetral]

haha, true
but, well, I made this only on software, I'm not planning to do that IRL, how would you make registers IRL? is there an other way than using a block of SRAM? obviously read 2 registers in one clock cylcle is easy, I'm just wondering if there's another way than adding a whole selection circuit.

[admin]

Sorry I don't know this. You probably can try to use some optimization software to minimize number of gates, but other than that you will probably need two decoders to decode two address at the same time if there is no any correlation between these two.

[Xaetral]

ok, thank you, that's what I wanted to hear; so I'll just modifiy the input selector, and we'll see if I manage to finish this V3.

[admin]

I understand it is not your goal but just our curiosity here I've built register block with two memory components. The write signal will write to both of them while when reading it will allow to read from two registers.

[Xaetral]

that's a nice circuit you've made there ^^; I've just finished all my thruth tables for my instruction decoder, I put it here if someone is curious.
(I don't expect anyone to understand it though XD)

[Xaetral]

I finished my instruction decoder v.3 so I'm working on the registers now; I deleted everything exept the I/O and I made modules this time



I think it's way cleaner now