Why so complicated?
Posted: Tue Jan 03, 2023 8:12 pm
A computer is not that complicated to make.(definitely not complicated that it needs >15 tutorials)
I'll post my way of doing it here using logisim evolution.(for the tutorial count,this is first one,the next one should be about optimizations,and the last video should be about extension stuff attached to bus using ram spoofing so there need only 3 tutorials)
First,there shall be a bus.It shall be 64 bits wide for my design.
There shall be a clock mechanism.In logisim,you can use an simple edge detection gate combination for clock multipling.The clock is connected to the cl tunnel.
Bus structure:every component has an output and a input that are connected to the bus.The output must be tristated using a controlled buffer(its called a tri-state outside the logisim world,cburch!)Every component has a load pin for latching,a store pin for outputting,and maybe a third pin for some additional function.Every component should be connected to the cl pin.
Next,there shall be 2 registers that lack an output pin for the operands,and one extra one for the operator.A mux should be connected to the operator output,instead of a dmx on both of the inputs.You can stuff a LOT of stuff from that arithmetic section here.Connect everything's inputs to the two operannds and their outputs to the mux.The "error" and "> = <" outputs can go to a splitter to join together for flags.(in my design the flags do not go to the control logic bc hard eeprom writing,they go to the bus)
Then,there shall be a counter connected like a register.the count enable pin should connect to an and gate of the control pin and the condition register output(also a register on the bus,1 bit)
Then,there shall be an instruction register connected normally,but output split into 4(in my design) the bottom 3 go tristate then back to bus,and the top goes to control logic
Then,we can connect an outputless register onto the bus as the memory address register,and its output to a ram module's address pin.the ram module should be connected like a register.(you would want the ram to be connected a bit outwards----or you will have a bit of trouble dismantling it and replacing it with a spoofer in part 3)
Finally,we can connect a counter to the clock and a PLA to the output.The PLA should get the instruction opcode and the counter.It should output control signals to all the control pins(load,store,activate on all stuff on the bus) and the reset pin of the counter.
Now program the PLA and we are finished!(no registers here,cuz in logisim you would end up with a structure alike the ram,so just use the ram,in real life the ram is faraway and it will cost time to go there so there are register stacks)
Part 2:optimizations
Actually,not much can be done here.You can overclock it by using edge detectors and make the pla controls more efficient.
Those optimizations except multi core processing in real life don't actually work with logicly(all are equivalent to overclocking)
Multi core processing will make about the same lag as overclocking.
Part 3:RAM spoofing
the ram is nice but you will want to connect external stuff to the cpu.
you can replace the ram with a chip that compares the input address to some endpoint values and gives the signals to the according device.its rather simple.ou just need a mux and several compareters.
my design:8m memory,8 numbers for (screen pixel x,screen pixel y,screen pixel rgb,mousex,mousey,screen clear,key,tty character),the rest are just unconnected to anything
I'll post my way of doing it here using logisim evolution.(for the tutorial count,this is first one,the next one should be about optimizations,and the last video should be about extension stuff attached to bus using ram spoofing so there need only 3 tutorials)
First,there shall be a bus.It shall be 64 bits wide for my design.
There shall be a clock mechanism.In logisim,you can use an simple edge detection gate combination for clock multipling.The clock is connected to the cl tunnel.
Bus structure:every component has an output and a input that are connected to the bus.The output must be tristated using a controlled buffer(its called a tri-state outside the logisim world,cburch!)Every component has a load pin for latching,a store pin for outputting,and maybe a third pin for some additional function.Every component should be connected to the cl pin.
Next,there shall be 2 registers that lack an output pin for the operands,and one extra one for the operator.A mux should be connected to the operator output,instead of a dmx on both of the inputs.You can stuff a LOT of stuff from that arithmetic section here.Connect everything's inputs to the two operannds and their outputs to the mux.The "error" and "> = <" outputs can go to a splitter to join together for flags.(in my design the flags do not go to the control logic bc hard eeprom writing,they go to the bus)
Then,there shall be a counter connected like a register.the count enable pin should connect to an and gate of the control pin and the condition register output(also a register on the bus,1 bit)
Then,there shall be an instruction register connected normally,but output split into 4(in my design) the bottom 3 go tristate then back to bus,and the top goes to control logic
Then,we can connect an outputless register onto the bus as the memory address register,and its output to a ram module's address pin.the ram module should be connected like a register.(you would want the ram to be connected a bit outwards----or you will have a bit of trouble dismantling it and replacing it with a spoofer in part 3)
Finally,we can connect a counter to the clock and a PLA to the output.The PLA should get the instruction opcode and the counter.It should output control signals to all the control pins(load,store,activate on all stuff on the bus) and the reset pin of the counter.
Now program the PLA and we are finished!(no registers here,cuz in logisim you would end up with a structure alike the ram,so just use the ram,in real life the ram is faraway and it will cost time to go there so there are register stacks)
Part 2:optimizations
Actually,not much can be done here.You can overclock it by using edge detectors and make the pla controls more efficient.
Those optimizations except multi core processing in real life don't actually work with logicly(all are equivalent to overclocking)
Multi core processing will make about the same lag as overclocking.
Part 3:RAM spoofing
the ram is nice but you will want to connect external stuff to the cpu.
you can replace the ram with a chip that compares the input address to some endpoint values and gives the signals to the according device.its rather simple.ou just need a mux and several compareters.
my design:8m memory,8 numbers for (screen pixel x,screen pixel y,screen pixel rgb,mousex,mousey,screen clear,key,tty character),the rest are just unconnected to anything