My first CPU Project (Daisuki)
Posted: Thu Oct 19, 2023 3:16 am
I just noted that I never posted my first CPU project.
Its name is "Daisuki" (Jap: "Big liking").
The CPU is in the category "cpu.ic". I first created "cpu" and ported it to "cpu.ic" based on 7400 series ICs, but later I changed some things in "cpu.ic" and did not touch "cpu" ever again, so I don't know if "cpu" is working and consistent.
It is just built to work, and not optimized for speed or fewer gates. A 4-bit CPU with an 8-bit address and data bus. Beside the PC, it contains a central accumulator register that is used in any except one command, 16 GPR, space for 16 instructions where actual 13 are in use, 16 ALU-Operations and 16 4-bit input and 16 4-bit flip-flopped output pins. It can only read from memory, but the inputs and outputs can be used to attach any device, like an SRAM, or just connect 1:1 to use as additional registers. It is a single-cycle-CPU, where one machine cycle = one clock cycle. On the falling clock edge, the PC increments and the command is loaded and decoded in one step. On raising edge, the CPU raises the right Flipflop clock wires to "submit" the result. The decoder is microcoded in a ROM. The upper nibble of an opcode is always the command, and the lower one is a value, which is either a direct used immediate or the address of a register.
Here are the instructions. I am not happy with them, but after it seemed to work, I lost my interest in this CPU and headed for bigger projects:
The ALU Operations are in the CPU File. I could not include them in the post ("Incorrect string value: '\xE2\x86\x92 ca...' for column 'post_text' at row 1 [1366]") and also not attach a text file.
The circuit "Multiplier" contains a test case where the CPU reads 2 8-bit values from input ports (0, 1) and (2, 3), multiples them just by an adding loop to a 16-bit result and sends it to output ports 0 - 4. It seems there was a bug and the result is undefined when input ports (2, 3) are all zero.
Its name is "Daisuki" (Jap: "Big liking").
The CPU is in the category "cpu.ic". I first created "cpu" and ported it to "cpu.ic" based on 7400 series ICs, but later I changed some things in "cpu.ic" and did not touch "cpu" ever again, so I don't know if "cpu" is working and consistent.
It is just built to work, and not optimized for speed or fewer gates. A 4-bit CPU with an 8-bit address and data bus. Beside the PC, it contains a central accumulator register that is used in any except one command, 16 GPR, space for 16 instructions where actual 13 are in use, 16 ALU-Operations and 16 4-bit input and 16 4-bit flip-flopped output pins. It can only read from memory, but the inputs and outputs can be used to attach any device, like an SRAM, or just connect 1:1 to use as additional registers. It is a single-cycle-CPU, where one machine cycle = one clock cycle. On the falling clock edge, the PC increments and the command is loaded and decoded in one step. On raising edge, the CPU raises the right Flipflop clock wires to "submit" the result. The decoder is microcoded in a ROM. The upper nibble of an opcode is always the command, and the lower one is a value, which is either a direct used immediate or the address of a register.
Here are the instructions. I am not happy with them, but after it seemed to work, I lost my interest in this CPU and headed for bigger projects:
Code: Select all
0000wxyz (0x0i) LDI LOAD acc WITH i
0001wxyz (0x1r) LDA LOAD acc WITH r
0010wxyz (0x2r) LDR LOAD r WITH acc
0011wxyz (0x3i) SAO SET ALU OPERATION
0100wxyz (0x4i) ALI EXECUTE ALU OPERATION ON acc AND i AND STORE THE RESULT IN acc
0101wxyz (0x5r) ALR EXECUTE ALU OPERATION ON acc AND r AND STORE THE RESULT IN acc
0110wxyz (0x6?)
0111wxyz (0x7?)
1000wxyz (0x8i) JPI JUMP TO ADDRESS (i << 4) | acc
1001wxyz (0x9r) JPR JUMP TO ADDRESS (r << 4) | acc
1010wxyz (0xAr) JRI JUMP TO (current address + i), WHERE i IS SIGN-EXTENDED TO 8 BIT
1011wxyz (0xBi) JPC JUMP TO (i << 4) | acc IF CARRY IS SET
1100wxyz (0xCr) JPZ JUMP TO (i << 4) | acc IF ZERO IS SET
1110wxyz (0xDi) WOU WRITE acc TO OUTPUT PORT i
1111wxyz (0xEi) RIN READ FROM INPUT PORT i AND STORES IN acc
1101wxyz (0xF?)
The circuit "Multiplier" contains a test case where the CPU reads 2 8-bit values from input ports (0, 1) and (2, 3), multiples them just by an adding loop to a 16-bit result and sends it to output ports 0 - 4. It seems there was a bug and the result is undefined when input ports (2, 3) are all zero.