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Hello there.

I have create a decoder, but I get an unexcepted output.

They excepted outputs are:
p should be the previouse output.

But for the test, i have deactivated 0b10101xyz (q = 0b00), 0b01110xyz (q=0b11) and p get constantly 1.



On the rising edge of the clock, the left D flipflop update the value from the ripped carry adder to the decoder (and the adders input). On the falling edge, the value from the decoder will update to the probe.
But sometimes I get on the probe the unexcepted value 0 for a short time.
Do anyone see whats there wrong? Because the decoder controll a multiplexer, I get in my main circuit a wrong result.

Thank you


(The "Extender" copy the incoming bit to all outgoing bits.)

I am sorry, but I do not understand what you are trying to build. If your goal is to implement truth table you have I’d suggest to synthesis it for each output bit separately as you normally do it.

Hello Volvagia,

I get your problem. This problem also occurs often in real life.
Mostly these problems are due to propagation delay times. Another important cause is the changing of counter-outputs.
The low to high transitions and the high to low transitions aren't equal.

First I have to say, that your way of thinking is entirely correct. I've figured out, that you would decode, if a number (address)
is within one of four numeric ranges (address ranges), After that you can, with the outcome, control a "n"-bit 4 -> 1 multiplexer. Am I right?
The difficulty of your design is the timing

The answers are in the attached file.
By the way, I've changed the decoding. Number 0 belongs to the lowest range (10H-17H), number 1 to range (38H-3FH), number 2 to range (70H-77H) and
number 3 to range (A8H-AFH)

I hope that you can continue your design now.
I'm very curious, what it's gonna be. Please let me now, if you've finished it.

Best Regards
Hans Cadans

Wow, thank you very very much.
It's should be a decoder in a finity state machine, which control a multiplexer when the FSM reach one of the states. (Or keep the multiplexer state on each other FSM state)
I will tell you, when (/if) the project reach an acceptable state.