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ld, st   ->   Load / Store indirect through register and offset e.g. ld r2, r1, 5  (r2 = Mem[r1 + 5])

add, sub, and, or, xor, shl, shr, rol, ror -> 3 registers ALU op e.g.  add r1, r2, r3 (r1 = r2 + r3)

add, and, or, xor -> immediate ALU op e.g. add r1, 5 (r1 = r1 + 5)

shl, shr, rol, ror -> shift with 2 registers and immediate e.g. shl r1, r2, 4 (r1 = r2 << 4)

beq, bne, bcs, bcc -> branch instructions with ofset e.g. bcc loop (branch if carry clear to loop)

addi -> add immediate e.g. addi r2, r1, 4  (r2 = r1 + 4), this is used for 'mov' instruction, see later

test -> test bit and set 'zero' flag, e.g. test r1, $80  (r1 & 0x80, test bit 7)

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ld, st  from address e.g  ld r1, 4 equivalent to ld r1, r0, 4

mov from register e.g. mov r1, r2 (r1 = r2) equivalent to add r1, r0,r2

mov from immediate e.g. mov r1, $F (r1 = 15) equivalent to addi r1, r0, 15

not e.g not r2 equivalent to xor r2, r2, $FF

clr clear e.g. clr r1 (r1 = 0) equivalent to and r1, r1, 0

inc, dec  e.g. inc r3 equivalent to add r3, r3, 1

cmp compare e.g. cmp r1, r2 (sub r0, r1, r2) and cmp r1, 5 equivalent to addi r0, r1, 256 - 5 (two's complement)

sub with immediate, e.g. sub r2, 8 equivalent to add r2, 256 - 8 (two's complement)

shift instructions with immediate e.g. rol r1, 2 equivalent to rol r1, r1, 2