Export to VHDL

[sir Kamba]

I was wondering if there is a function to export to VHDL, verilog or some other hardware description language?
I would like to test my CPU design on a fpga when i'm done designing it.
but before i get to do that, i have to finish the design (i have a working prototype, albeit in a smaller scope) and learn to use a fpga.
Ideally i would like to build my own computer using only gates, but coming up on 15k gates of varying sizes, a fpga seems like the more reasonable option.

Anyways, keep up the good work.

[admin]

Hi,
No there is no export to Verilog. Could be an interesting feature to add though.
Regards,
Eugene

[sir Kamba]

Okay, it's been a while and i have decided that I am going to implement it myself.
C# is not my language of choice and as such I can't go into the source code of logiccircuit and implement it myself (I have looked at it).
the second best option is to reverse engineer the .CircuitProject files and make a convertion program. This is fairly easy as .CircuitProject files are simply .xml files.

So far i have parsed the files, grouped content by LogicalCircuitId and built the netlist.
Next would be mapping CircuitSymbol to correct components and getting the locations of each of the pins on the symbol which is hard when the sizes of the symbols are not stored but generated on load. Any advice?

Another problem is that when a field is the default value, it is simply omitted from the file.
And how is the rotation of a symbol saved?

Once those problems are solved i can begin to convert each circuit to verilog modules and start optimizing.
I do intend to either omit or use placeholder modules for certain components such as the buzzer or sensors as they are not possible synthesize.

Also here is a list of the static UUID for some of the components.

Code: Select all

	["00000000-0000-0000-0000-0000000b0200"]="TRILEFT";
	["00000000-0000-0000-0000-0000000a0200"]="TRIRIGHT";

	["00000000-0000-0000-0000-000000020101"]="NOT";

	["00000000-0000-0000-0000-000000030200"]="OR2";
	["00000000-0000-0000-0000-000000030300"]="OR3";
	["00000000-0000-0000-0000-000000030400"]="OR4";
	["00000000-0000-0000-0000-000000030500"]="OR5";
	["00000000-0000-0000-0000-000000030600"]="OR6";
	["00000000-0000-0000-0000-000000030700"]="OR7";
	["00000000-0000-0000-0000-000000030800"]="OR8";
	["00000000-0000-0000-0000-000000030900"]="OR9";
	["00000000-0000-0000-0000-000000030a00"]="OR10";
	["00000000-0000-0000-0000-000000030b00"]="OR11";
	["00000000-0000-0000-0000-000000030c00"]="OR12";
	["00000000-0000-0000-0000-000000030d00"]="OR13";
	["00000000-0000-0000-0000-000000030e00"]="OR14";
	["00000000-0000-0000-0000-000000030f00"]="OR15";
	["00000000-0000-0000-0000-000000031000"]="OR16";
	["00000000-0000-0000-0000-000000031100"]="OR17";
	["00000000-0000-0000-0000-000000031200"]="OR18";

	["00000000-0000-0000-0000-000000030201"]="NOR2";
	["00000000-0000-0000-0000-000000030301"]="NOR3";
	["00000000-0000-0000-0000-000000030401"]="NOR4";
	["00000000-0000-0000-0000-000000030501"]="NOR5";
	["00000000-0000-0000-0000-000000030601"]="NOR6";
	["00000000-0000-0000-0000-000000030701"]="NOR7";
	["00000000-0000-0000-0000-000000030801"]="NOR8";
	["00000000-0000-0000-0000-000000030901"]="NOR9";
	["00000000-0000-0000-0000-000000030a01"]="NOR10";
	["00000000-0000-0000-0000-000000030b01"]="NOR11";
	["00000000-0000-0000-0000-000000030c01"]="NOR12";
	["00000000-0000-0000-0000-000000030d01"]="NOR13";
	["00000000-0000-0000-0000-000000030e01"]="NOR14";
	["00000000-0000-0000-0000-000000030f01"]="NOR15";
	["00000000-0000-0000-0000-000000031001"]="NOR16";
	["00000000-0000-0000-0000-000000031101"]="NOR17";
	["00000000-0000-0000-0000-000000031201"]="NOR18";

	["00000000-0000-0000-0000-000000040200"]="AND2";
	["00000000-0000-0000-0000-000000040300"]="AND3";
	["00000000-0000-0000-0000-000000040400"]="AND4";
	["00000000-0000-0000-0000-000000040500"]="AND5";
	["00000000-0000-0000-0000-000000040600"]="AND6";
	["00000000-0000-0000-0000-000000040700"]="AND7";
	["00000000-0000-0000-0000-000000040800"]="AND8";
	["00000000-0000-0000-0000-000000040900"]="AND9";
	["00000000-0000-0000-0000-000000040a00"]="AND10";
	["00000000-0000-0000-0000-000000040b00"]="AND11";
	["00000000-0000-0000-0000-000000040c00"]="AND12";
	["00000000-0000-0000-0000-000000040d00"]="AND13";
	["00000000-0000-0000-0000-000000040e00"]="AND14";
	["00000000-0000-0000-0000-000000040f00"]="AND15";
	["00000000-0000-0000-0000-000000041000"]="AND16";
	["00000000-0000-0000-0000-000000041100"]="AND17";
	["00000000-0000-0000-0000-000000041200"]="AND18";

	["00000000-0000-0000-0000-000000040201"]="NAND2";
	["00000000-0000-0000-0000-000000040301"]="NAND3";
	["00000000-0000-0000-0000-000000040401"]="NAND4";
	["00000000-0000-0000-0000-000000040501"]="NAND5";
	["00000000-0000-0000-0000-000000040601"]="NAND6";
	["00000000-0000-0000-0000-000000040701"]="NAND7";
	["00000000-0000-0000-0000-000000040801"]="NAND8";
	["00000000-0000-0000-0000-000000040901"]="NAND9";
	["00000000-0000-0000-0000-000000040a01"]="NAND10";
	["00000000-0000-0000-0000-000000040b01"]="NAND11";
	["00000000-0000-0000-0000-000000040c01"]="NAND12";
	["00000000-0000-0000-0000-000000040d01"]="NAND13";
	["00000000-0000-0000-0000-000000040e01"]="NAND14";
	["00000000-0000-0000-0000-000000040f01"]="NAND15";
	["00000000-0000-0000-0000-000000041001"]="NAND16";
	["00000000-0000-0000-0000-000000041101"]="NAND17";
	["00000000-0000-0000-0000-000000041201"]="NAND18";

	["00000000-0000-0000-0000-000000050200"]="XOR2";
	["00000000-0000-0000-0000-000000050300"]="XOR3";
	["00000000-0000-0000-0000-000000050400"]="XOR4";
	["00000000-0000-0000-0000-000000050500"]="XOR5";
	["00000000-0000-0000-0000-000000050600"]="XOR6";
	["00000000-0000-0000-0000-000000050700"]="XOR7";
	["00000000-0000-0000-0000-000000050800"]="XOR8";
	["00000000-0000-0000-0000-000000050900"]="XOR9";
	["00000000-0000-0000-0000-000000050a00"]="XOR10";
	["00000000-0000-0000-0000-000000050b00"]="XOR11";
	["00000000-0000-0000-0000-000000050c00"]="XOR12";
	["00000000-0000-0000-0000-000000050d00"]="XOR13";
	["00000000-0000-0000-0000-000000050e00"]="XOR14";
	["00000000-0000-0000-0000-000000050f00"]="XOR15";
	["00000000-0000-0000-0000-000000051000"]="XOR16";
	["00000000-0000-0000-0000-000000051100"]="XOR17";
	["00000000-0000-0000-0000-000000051200"]="XOR18";

	["00000000-0000-0000-0000-000000050201"]="XNOR2";
	["00000000-0000-0000-0000-000000050301"]="XNOR3";
	["00000000-0000-0000-0000-000000050401"]="XNOR4";
	["00000000-0000-0000-0000-000000050501"]="XNOR5";
	["00000000-0000-0000-0000-000000050601"]="XNOR6";
	["00000000-0000-0000-0000-000000050701"]="XNOR7";
	["00000000-0000-0000-0000-000000050801"]="XNOR8";
	["00000000-0000-0000-0000-000000050901"]="XNOR9";
	["00000000-0000-0000-0000-000000050a01"]="XNOR10";
	["00000000-0000-0000-0000-000000050b01"]="XNOR11";
	["00000000-0000-0000-0000-000000050c01"]="XNOR12";
	["00000000-0000-0000-0000-000000050d01"]="XNOR13";
	["00000000-0000-0000-0000-000000050e01"]="XNOR14";
	["00000000-0000-0000-0000-000000050f01"]="XNOR15";
	["00000000-0000-0000-0000-000000051001"]="XNOR16";
	["00000000-0000-0000-0000-000000051101"]="XNOR17";
	["00000000-0000-0000-0000-000000051201"]="XNOR18";

dumpFile.txt contains a dump of the memory structure of "Circuit Project.CircuitProject" after parsing.

[Xaetral]

I don't know anything about verilog (expect it's like the US version of VHDL) but I learned VHDL.

I think it would be easy to convert files from LC to VHDL files, as there are a lot of common things:
- cicuits and subcircuits are easily defined by "entity"
- I/O can be put inside "entity" with the keyword "port"
- I/O with multiple bits are available with the keywords "STD_LOGIC_VECTOR" and "downto" (or "upto", less used)
- ROM are easily defined with some LUT, writen with a "switch" in the vhd file

however I think there are some things that we can improve, like use pre-made vhd like D flip-flops and registers, arithmetic libraries, etc

in a perfect world, these blocs and the convertion to verilog or vhdl should be inside LC, like the flips-flops in logicly or the arithmetic blocs in logisim

anyway, it would be a nice feature ^^

[sir Kamba]

I became inspired to do something a few days ago, and decided to convert .CircuitProject files to vhdl.

Today I got the first successful test. The code is not very good, and it only handles a subset of what logiccircuit can do.
it does not infer registers and flip flops. and does not handle memories for now.
any graphics elements is not supported, and probably never will be. I might utilize an empty wrapper for these types of components.

This is the first draft and I will improve on it in the future.

PS: I have not been working on this since 2016.