Problem with FLIP FLOP async clk counter

[elak]

Hi, I have problems with T flip flops,

When I use them alone, nothing wrong but when i want to countdown with the output from the first one used for the second one input clock , sometimes I have unexpected outputs,not always, it's really random ... and anoying.
I tried to do My own T flip flop, I used the one in the samples, no matter the one I use, I always have some unexpected random results.

could someone explain me where I am wrong ... is this a feature ( bug) ?

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testD.CircuitProject

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elak

[admin]

Hi Elak,
The problem is in your Bascule D FM. If you trying to build positive edge D flip-flop you will need a bit more complicated circuitry. Please start with this wiki section:
https://en.wikipedia.org/wiki/Flip-flop ... _flip-flop
In your design, you are trying to detect front edge in unreliable way hoping for delay on 3 invertors. This is not going to work in all cases, and that exactly what you observing.
Can you also try to reason on why do you want front edge flip-flop? If you building counter then it is more natural to use master-slave rear edge flip-flops as the flip on the next bit should only occurred when previous is going down. For that matter you can look at the samples in clock there are counters that work that way.
Regards,
Eugene