Output LogicCircuit designs to HDL and VHDL

[jkb]

I have developed a version of LogicCircuit (branched from current source - Release_2.21.01.10) that saves to Nand2Tetris HDL or to structural VHDL (for use with an FPGA design tool such as Xilinx Vivado).
Installer, source, and docs at:
https://github.com/jkb-git/LogicCircuit-to-HDL-or-VHDL
john

[ap2014]

Thanks for sharing