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Its been a while, but the reason why it was suboptimal was that at the time when I was testing out the circuit. I was not able to get any proper behaviour from it unless I used many not gates, like 15 of them. Although it was more a flaw of how I was debugging it and testing it. I'm using three not ...

Is it possible to control the propagation delay of ports? The way CEDAR logic simulator does it?

The reason I ask is because I want to implement a pulse transition detector, but it seems the propagation delay is set very low in this program. I can get it kinda working by chaining several gates in a ...