Is it possible to control the propagation delay of ports? The way CEDAR logic simulator does it?
The reason I ask is because I want to implement a pulse transition detector, but it seems the propagation delay is set very low in this program. I can get it kinda working by chaining several gates in a row, but its a suboptimal solution.
An implementation of this would make this program the ultimate logic gate simulator!
Hi,
Currently it is not possible to adjust delay of the gates. But as you’ve mentioned you can chain 3 inverters to get behavior you need.
Why do you think it is suboptimal? What do you think going to happened in the real life in such cases? Do you think it will be enough to have just one inverter in real life circuit?
Thanks,
Eugene
Its been a while, but the reason why it was suboptimal was that at the time when I was testing out the circuit. I was not able to get any proper behaviour from it unless I used many not gates, like 15 of them. Although it was more a flaw of how I was debugging it and testing it. I'm using three not gates now and its working fine, so it was more like a lack of understanding on my part.
I have a new question though. In the newest version when I set the notation on an input pin that is on the left or right side of the circuit symbol, only two characters appear. For inputs that are either top or bottom there can be more. Is there a specific reason for this? I would for instance want to label an input clk without having it become cl. I've seen on the forums that other users have had circuits that have more than two character on their labelling, so I'm not sure if I'm failing hard or what is happening with that.
Yes, you are right the notation of the pin is truncated to 2 characters if it resides on the left or right sides and to 4 for top and bottom. The reason for this is small amount of space for the text on the symbol.
You can use not only letters and digits there though. For example for the clock input instead of "clk" you can use greater sign ">" which fairly common.
