0-159 Counter please help!
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rjryurimida1896
- Posts: 1
- Joined: Fri May 19, 2017 8:42 pm
0-159 Counter please help!
have a logic circuit project. And it needs to count 0-159 then reset after. I have a schematic diagram Ive made so far I have attached it in this post and I used 555 timer, 7493 and 4511 ICs but IT ONLY COUNTS 0-199 and I don't know how to make it just 159. Please help.
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Hans Cadans
- Posts: 57
- Joined: Thu Apr 24, 2014 12:30 pm
Re: 0-159 Counter please help!
Best rjryurimida1896,
I've seen your question earlier, but I've forgotten to answer.
Today I saw your problem again.
In case of, you did not found the solution, yourself, or you did not receive an answer,
I propose you this solution.
The counter, which counts the tens, is reset by the combination of d8 AND d2 (together 10).
Also the output of this AND-gate is used as the clock for the hundreds.
Add an OR-gate between this reset-signal and between the clock-signal,
and connect the output of the existing AND-gate to one of the inputs of the OR-gate.
With a triple-input AND-gate, you have to decode the d4 and d2 output of the counter for the tens. (together 6)
At last you have to connect the d2 output of the hundreds to the remaining input of the triple-AND-gate.
Connect the output of this gate to the remaining input of the OR-gate.
Best Regards,
Hans Cadans
I've seen your question earlier, but I've forgotten to answer.
Today I saw your problem again.
In case of, you did not found the solution, yourself, or you did not receive an answer,
I propose you this solution.
The counter, which counts the tens, is reset by the combination of d8 AND d2 (together 10).
Also the output of this AND-gate is used as the clock for the hundreds.
Add an OR-gate between this reset-signal and between the clock-signal,
and connect the output of the existing AND-gate to one of the inputs of the OR-gate.
With a triple-input AND-gate, you have to decode the d4 and d2 output of the counter for the tens. (together 6)
At last you have to connect the d2 output of the hundreds to the remaining input of the triple-AND-gate.
Connect the output of this gate to the remaining input of the OR-gate.
Best Regards,
Hans Cadans