Logical zero produced by circuit not equal to constant zero leading to incorrect behaviour?

[joseph_f2]

Hey everyone,

First post here, so I may be missing something pretty obvious, but I've been trying to get some master slave JK flipflops to work as intended. I've jumped through the majority of the hops (e.g. reset states) and this has been good enough so far. However, I believe I've encountered a bug (possibly due to how circuits are initially converted into boolean expressions upon power on?).

I've copied out the problematic circuit from my project and attached it below. The issue is that flipflops initialised with a logical zero produced by a circuit react differently than those initialised by a constant logical zero produced by the 'Constant' IO primitive. You may need to run it a few times, but notice each side does not yield the same result. Instead, the right remains correct, whereas, the left does not.

To make things easier to understand, here's a rundown of what is included in the project:
* 'ANDer' - Performs an 'and' operation on two 8-bit inputs.
* 'SP' (Single Pulse) - Produces a single clock pulse once and never again.
* 'CLK' (Clock) - A clock circuit which produces a logical one as per normal, expect for very first pulse of the 'Clock' element.
* 'PS' (Pin Select) - Takes a constant input value and chooses that pin from the input bus. E.g. select pin 4 of b0000 <1>011.
* '2X4' - 2 by 4 decoder.
* '3X8' - 3 by 8 decoder. Decoders are used by the Pin Select ('PS') circuit.
* '2E' (2 Bit Enabler) - Passes through input if enable line is switched on.
* '4E' (4 Bit Enabler) - Passes through input if enable line is switched on.
* 'LD' (Latch Delay) - After X clock circuits, enable output and stay on.
* 'MS JK' (Master Slave JK) - Flipflop, basically just a massive headache due to acting on both rising and falling edge of clock cycle :( If someone has a better way to build these so they can be reset in a single clock circuit properly, please tell me.
* 'Main' - Finally, the main container of all of these circuits. The JKs on the left get their clear ('clr') signal from another circuit, and the ones on the right get their signal from a constant logical zero. Really anything could have been used instead of my latch delay ('LD') circuit, but I needed a way to intentionally wait a number of clock circuits to ensure everything should be setup in its intended state.

[admin]

Try to reset your master one too

[joseph_f2]

Unfortunately, I had no luck adding an additional reset to the other part of the JK. It's worth noting, even a simple setup like the one pictured in the attached image produces the same odd results. I've got a workaround in mind, so I'll give that a go.

Perhaps it would be possible to remove the element of randomness from the codebase which causes this kind of behaviour? I think it'd be nice to have the option to disable this.

[admin]

I am not sure I understand what the problem is. It will help if you explain it in more details with the project file that demonstrate it.